1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure capable of easily identifying from an outside of the semiconductor device whether or not an inner circuit is placed under predetermined operating conditions. This invention also relates to a structure for externally identifying whether or not an internal state of a semiconductor device is set so as to satisfy predetermined test conditions.
2. Description of the Related Art
A semiconductor device undergoes various tests after its manufacture to ensure the reliability. As such tests, a burn-in test, an acceleration test employed in a life test or the like, and an operating margin test, etc. are known.
Since an operating power source voltage is set greater than that at the time of the normal operation upon the burn-in test, stress placed on an inner circuit is increased. By activating the semiconductor device under this condition, characteristics of components in the inner circuit are stabilized and a screening (removal of an initial failure) is performed through the revelation of a potential failure. In the case of the acceleration test, the operating power source voltage is similarly raised and operating environments (operating temperature, humidity) are made severe as compared within the normal operation. Under this condition, a period during which the semiconductor device is normally operated is measured. Upon the operating margin test, the power source voltage is slightly reduced as compared within the normal operation. Under this condition, a test is made as to whether or not the semiconductor device is normally operated. As the operating margin test, there are known a test for checking, whether or not a dynamic semiconductor memory device with memory cells including capacitors is accurately storing data by reducing a voltage written into a memory cell capacitor and writing data therein and then reading data therefrom, a test for checking whether or not an access time or the like satisfies a predetermined rated value even when an operating voltage is reduced.
FIG. 20 is a diagram schematically showing the overall structure of a conventional semiconductor device. In FIG. 20, the conventional semiconductor device 900 includes a power pin terminal 902 supplied with an external power source voltage VCE, a ground pin terminal 904 supplied with a ground voltage VSS, a power source line 905 connected to the power pin terminal 902 so as to supply a voltage, a ground line 907 connected to the ground pin terminal 904 so as to supply a ground voltage, an internal voltage down converter 910 which operates with the external power source voltage VCE on the power source line 905 and the ground voltage VSS on the ground line 907 as operating power source voltages and serves so as to supply an internal power source voltage VCI having a predetermined level to an internal power source line 909 when the external power source voltage VCE is within a predetermined range, an internal power source voltage utilizing circuit 912 which operates with the internal power source voltage VCI on the internal power source line 909 and the ground voltage VSS on the ground 907 as operating power source voltages and serves so as to execute a predetermined function, and an input/output buffer 914 which operates with the power source voltage VCE on the external power source line 905 and the ground voltage VSS on the ground line 907 and serves so as to input and output a signal (including data) between the internal power source voltage utilizing circuit 912 and the outside of the semiconductor device. In the structure shown in FIG. 20, the semiconductor device 900 may includes a circuit which operates with externally applied power source voltage VCE and a ground voltage VSS as operating power source voltages, so as to execute a predetermined function. Since internal circuitry of the semiconductor device is operated based on the internal power source voltage VCI, the input/output buffer 914 is supplied with the power source voltage VCE for interfacing.
The reason for allowing the internal voltage down converter 910 to reduce the externally supplied power source voltage VCE to produce the internal power source voltage VCI is as follows:
Components or elements are subject to miniaturization or micronization with progress of high integration of the semiconductor device. A power source voltage level is reduced in accordance with a scaling rule, for example, to ensure the reliability of the sub-micronized components and to reduce power consumption. However, the semiconductor device is not singly used and a plurality of kinds of semiconductor devices are used upon constructing a system. A logic LSI (Large-Scale Integrated) circuit, a processor and a semiconductor memory device are different in integration progress speed and element-micronization progress speed from each other. It is thus necessary to use, as a system power source voltage, a voltage determined by the LSI in which the element micronization progress speed is the slowest. Since the micronization progress speed of the semiconductor memory devices is the fastest, a power source voltage higher than an internal power source voltage necessary for the semiconductor memory devices is used as an external power source voltage. Therefore, the internal voltage down converter 910 is provided to reduce the external power source voltage VCE and produce the internal power source voltage VCI lower the external power source voltage VCE inside the semiconductor device. Owing to the provision of such an internal voltage down converter 910, a system using a single system power source can be constructed using a plurality of kinds of LSIs different in operating power source voltage from each other.
FIG. 21 is a block diagram showing the structure of an internal voltage down converter shown in FIG. 20. In FIG. 21, an internal voltage down converter 910 includes a reference voltage generating circuit 922 for generating a reference voltage Vref having a predetermined level, a drive transistor 924 composed of a p channel MOS transistor (insulated gate type field effect transistor) for supplying current to an internal power source line 909 to generate an internal power source voltage VCI from an external power source voltage VCE supplied to a power source line 905, and a comparator 926 for comparing the internal power source voltage VCI on the internal power source line 909 and the reference voltage Vref generated from the reference voltage generating circuit 922 and adjusting the conductance of the drive transistor 924 in accordance with the result of comparison. The comparator 926 receives internal power source voltage VCI at a positive input and reference voltage Vref at a negative input.
The internal voltage down converter 910 further includes an n channel MOS transistor 928 which is brought conductive in response to a burn-in mode designation signal BI as an internal state setting signal to electrically connect an output node 929 of the comparator 926 and a ground line 907 to each other. Owing to the provision of the MOS transistor 928, the drive transistor 924 is forcedly brought into a conducting state to equalize the internal power source voltage VCI and the external power source voltage VCE to each other, thereby setting the internal power source voltage VCI to a desired voltage level.
An internal power source voltage utilizing circuit 912 includes a load circuit 912a operating with the internal power source voltage VCI on the internal power source line 909 and a ground potential on a ground line 907 as operating power source voltages. The internal power source voltage utilizing circuit 912 includes a plurality of kinds of load circuits 912a for respective functions, to which the internal power source voltage is supplied through different interconnection lines (for the stabilization of the internal power source voltage due to the dispersion of loads on the power source lines). Therefore, the load circuit 912a included in the internal power source voltage utilizing circuit 912 is representatively shown in FIG. 21. The operation of the circuitry of FIG. 21 will now be described in brief.
In the normal operating mode, the burn-in mode designation signal as the internal state setting signal (hereinafter called simply "burn-in mode designation signal") BI is at a low level indicative of an inactive state and the MOS transistor 928 is in an off state. In this state, the drive transistor 924 supplies a current to the internal power source line 909 in response to the potential on the output node 929 of the comparator 926 to generate the internal power source voltage VCI. When the internal power source voltage VCI is higher than the reference voltage Vref, the potential at the output node 929 of the comparator 926 is raised so that the conductance of the drive transistor 924 is reduced. Thus, the current (drain current) supplied from the drive transistor 924 is reduced so that an increase of the internal power source voltage VCI is stopped.
When the load circuit 912a is activated and the internal power source voltage VCI on the internal power source line 909 is reduced and becomes lower than the reference voltage Vref due to a leakage current on the internal power source line 909, a signal potential supplied to the output node 929 from the comparator 926 is reduced. Thus, the conductance of the drive transistor 924 is made greater to allow the drive transistor 924 to supply a large current to the internal power source line 909, and the internal power source voltage VCI is raised. Owing to a feedback loop formed by the comparator 926, the drive transistor 924 and the internal source line 909, the internal power source voltage VCI on the internal power source line 909 is brought to a voltage level determined by reference voltage Vref. The internal power source voltage VCI is normally made equal to the reference voltage Vref.
When a test operation is effected on the internal voltage down converter, the burn-in mode designation signal BI is set to an "H" indicative of an active state. At this time, the MOS transistor 928 is turned on so that the potential of the gate of the drive transistor 924 (the potential at the node 929) is forcedly brought to a ground potential level. Thus, the drive transistor 924 is brought conductive regardless of the output potential of the comparator 926 so as to supply the external power source voltage VCE to the internal power source line 909. As a consequence, the internal power source voltage VCI varies in accordance with the external power source voltage VCE.
FIG. 22 is a diagram for illustrating a relationship between an external power source voltage VCE and an internal power source voltage VCI. In FIG. 22, the axis of abscissa represents an external power source voltage and the axis of ordinate shows a voltage value. When the external power source voltage VCE is raised from the initial state, the reference voltage Vref generated from the reference voltage generating circuit 922 is also raised. Correspondingly, the internal power source voltage VCI increases as well. When the external power source voltage VCE reaches a predetermined value V0, the reference voltage Vref is brought to a constant value. Thus, the internal power source voltage VCI is maintained at a constant value for the level of the external power source voltage VCE which is more than or equal to the predetermined value V0. In the normal operation, an external power source voltage VCE in a voltage region ranging from V0 to V1 indicated as "normal usage region" in FIG. 22 is supplied to activate the semiconductor device. In this condition, the burn-in mode designation signal BI is at an "L" level.
When the burn-in mode designation signal BI is "H" level, the internal power source voltage VCI is raised in accordance with the external power source voltage VCE. In the burn-in mode test, the external power source voltage VCE is generally set to a voltage level between voltages V2 and V3. In order to vary the internal power source voltage VCI according to the external power source voltage VCE, two methods are proposed: a method of setting the burn-in mode designation signal BI to the "H" when the internal power source voltage VCI is a constant voltage (reference voltage Vref) level, and a method of setting the burn-in mode designation signal BI to the "H" when the external power source voltage VCE is reduced to the predetermined value V0 or less and then varying the internal power source voltage VCI in accordance with the external power source voltage VCE. FIG. 22 shows a level of an internal power source voltage VCI in a region (indicated as a "stress region" in FIG. 22) in which the burn-in mode designation signal is simply generated and the burn-in mode test is executed under this condition.
By setting the internal power source voltage VCI higher than that at the time of the normal operation, stress placed on components of the internal power source voltage utilizing circuit 912 is increased. Under this condition, a potential failure screening is performed.
By making use of the internal voltage down converter having the aforementioned construction, the internal power source voltage VCI can be varied according to the external power source voltage VCE even in other test operation as well as in the burn-in mode test so as to be set to a desired voltage level.
A test such as a burn-in mode test or the like is a final test prior to shipping of semiconductor devices and is also a non-destructive inspection. Namely, the semiconductor device is tested in a state of being accommodated within a package. In general, the test on the semiconductor device such as the burn-in mode test is not performed for each semiconductor device singly but is carried out on a plurality of semiconductor devices as a single unit.
FIG. 23 shows an arrangement of semiconductor devices in a burn-in mode test. In FIG. 23, a plurality of semiconductor devices (chips) CH00 through CHmn are disposed on a test board 950. Although the semiconductor devices are represented as "chips" in FIG. 23, they are accommodated in a package by resin sealing or the like, not in the form of flip chips.
Further, a monitor flip chip 952 fabricated in the same batch as that of the semiconductor devices CH00 through CHmn, is disposed on the test board 950. In the flip chip 952, pads PDs and inner circuits on which a sealing resin forming a package has been removed, have been exposed. The pads PDs are connected to corresponding external pin terminals PT by bonding wires BD. The pin terminals PT of the flip chip 952 are identical in arrangement to the semiconductor devices CH00 through CHmn. Further, a testing apparatus 960 is provided which applies a voltage to the test board 950 in a predetermined sequence, operates the semiconductor devices CH00 through CHmn and the flip chip 952 and analyzes the result of their operations.
A check apparatus 962 is provided corresponding to the flip chip 952. The check apparatus 962 detects a potential at an internal node ND of the flip chip 952 using a probe PB and checks whether or not the flip chip 952 has been set to a predetermined internal state. The check apparatus 962 may be included in the testing apparatus 960. To clearly show a test arrangement, the testing apparatus 960 and the check apparatus 962 are shown being provided separately from each other. A test operation will now be described.
Under the control of the testing apparatus 960, a burn-in mode designation signal BI is supplied to each of the semiconductor devices CH00 through CHmn and the monitor flip chip 952 all placed on the test board 950. The check apparatus 962 detects a potential at the predetermined node ND (corresponding to the output node 929 in FIG. 21, for example) of the monitor flip chip 952, using the probe PB. When the check device 962 detects the potential at the node ND, which has been brought to a predetermined potential (e.g., a ground potential), the corresponding nodes of all the semiconductor devices CH00 through CHmn are considered to be at predetermined potential levels and an external power source voltage VCE is raised by the testing apparatus 960, whereby the burn-in test is effected on each of the semiconductor devices CH00 through CHmn.
When it is desired to perform the burn-in test as described above, it is necessary to fabricate the monitor flip chip 952. The monitor flip chip 952 is fabricated by selecting a semiconductor device within the same batch as that of the semiconductor devices CH00 through CHmn to be tested and by removing a sealing resin that is a package for accommodating the selected semiconductor device therein. Therefore, a problem arises that much labor is required to fabricate the monitor flip chip 952, so that the burn-in test cannot be efficiently performed. Further, a problem arises that the monitor flip chip 952 is not recycled and shipped as a product due to the removal of a whole package, resulting in poor product efficiency.
A problem also arises that since internal states of the semiconductor devices CH00 through CHmn to be tested are determined by identifying the internal state (the potential at the predetermined node ND) of the monitor flip chip 952, even in the case where the semiconductor devices CH00 through CHmn to be tested have not been accurately set to desired internal states due to variations in operating parameters between the chips, they are erroneously determined to be set to the desired internal states, and may be subject to a test, whereby the accurate test cannot be ensured.
Further, a problem arises that it is necessary to provide the check apparatus 952 for detecting the potential at the predetermined node of the monitor flip chip, thereby causing an increase in the scale of the testing system. In addition to the above problem, a problem also arises that a dedicated jig is required to detect the potential at the predetermined node of the monitor flip chip, thereby causing an increase in the cost of the testing system.
Furthermore, a problem arises that when it is desired to test an operating margin or the like of a semiconductor device as well as a normal burn-in test, it is not possible to accurately identify whether or not an internal state of the semiconductor device accommodated in a package has been set to a predetermined state, whereby difficulties are encountered in accurately evaluating operating characteristics.